VSD - Custom Layout (Udemy.com)

VLSI - This is where design meets fabrication

Created by: Kunal Ghosh

Produced in 2016

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What you will learn

  • Draw layout from scratch, i.e. right from tech files to metal layer
  • Understand each and every mask level, through appropriate fabrication steps
  • Get to know how physical design flow communicates with CMOS fabrication process
  • This is how 2 different industries communicate

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Quality Score

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Overall Score : 90 / 100

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Course Description

Physical designers and CMOS fabrication team communicates with each other, and this course says it 'How?'
While physical designers use all the outputs from experiments performed by fabrication department, this course will demonstrate the best of both worlds and connect them through exchange of certain files in certain format
This way, custom layout designers get to know an insight how does fabrication works, fabrication engineers get to know, how layout engineers uses their information. So this course is a place where both meet, talk and connect.
Also, the standard files needed to draw and simulate layout, are being taken, deduced and created from scratch and on the fly. This is, by far, the best way to understand layout, and I can promise you an exciting journey throughout this course
Course is structured to explain the CMOS packaging and fabrication steps in beginning, followed by software and files used to draw and simulate layout, and look into DRC rules.
Next, we will take a simple CMOS inverter and apply all concepts learned above. Finally, we will learn the 'Art of layout' using Euler's path. This is where you will solve complex functions and draw a layout out of it.
Welcome you all to my course and Happy Learning!!
See you in class!Who this course is for:
  • Anyone curious to know the inception of layout
  • Anyone curious to know the software behind layout drawing
  • Anyone who wants to know how chip designers talk with chip fabrication department

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Instructor Details

Kunal Ghosh

Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal heldseveral technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.

Hands on with Technology @
1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP's and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.
2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.
3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.
5) "IR aware STA"

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Reviews

4.5

24 total reviews

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Average/Good. Could be better

Its great.Just giving 4.5 as there is always a room for improvement.

excellent lecture

Great intro to VSD Custom Layout. I am an EEII, transitioning from Aerospace to the VLSI Industry, with a BS in Electrical Engineering and feel that, though my undergrad microelectronics courses were taught in great detail, they went into so much low level detail that I did not get this level of "Top Level to Bottom Level" understanding from them.Before taking this course I took the following courses from the VSD series:- VSD Physical Design Flow- Clock Tree Synthesis Part I- Clock Tree Synthesis Part II- Signal Integrity- STA Part IThis course is definitely worth taking.I intend on continuing to take this instructor's courses in the order he recommends on his website.I would recommend this course to someone starting in VSD.

Impressed! This course definitely filled the gaps in my understanding how designer tools and foundry communicate and liked the concept of making use of euler path/circuit for optimized layout. I must appreciate the instructor's skills explaining every minute details in a brisk fashion. Looking eagerly for part-2.

By Ali on

Great course! CMOS fabrication process and Art of layout using Euler's path plus Stick diagram very well explained. DRC part covers main aspects of DRC rule deck. I highly recommend this course for anyone interested in layout design/CMOS fabrication process.

Very clear, detailed and one of the finest for both beginners and intermediates. DRC Rule check has been in detail. I strongly recommend.

Great Course. Good for them who are starting with designing.Personally I think, more examples or exercises should be there.But all in all nice course.Thanks Kunal!! Keep sharing your knowledge.

Very informative and clear. It was really helpful. Thank you!

nice course... good learning in quick time.

I loved the way he gave simple explanations for every slide. Awesome for beginners.

audio of some video's is not good