Digital RTL design and Verilog interview questions (Udemy.com)

Interview guide for logic design / RTL design / Setup and hold/ Verilog / Clock domain crossing

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Created by: Kiran Bhaskar

Produced in 2021

What you will learn

Verilog , RTL design concepts , Setup and hold questions , clock domain crossing concepts , Synchronizers , Divide by circuits

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Course Description

gital RTLdesign and Verilog interview questions is an initiative to help students/professionals who have basic knowledge of digital design and Verilog knowledge to quickly ramp up for an interview .
The course is structured as 6 part series addressing the following interview question/concepts .
Logic design and encoding Interview questionsSynthesizable verilog interview questionsSetup and hold interview questionsClock domain crossing interview questionsSynchronizers interview questions part1 - MTBF , 2FF synchronizer , 3FF synchronizerSynchronizers interview questions part2 -Synchronizer with feedback, Mux recirculation , Divide by 2 ,3 ,4 circuitsWho this course is for:
Beginner Digital design Engineers

Time: 39 mins on-demand videoh

Instructor Details

Kiran Bhaskar

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Extensive working experience in ASIC flow, IP/SOC Verification and Validation. Expertise in development of reusable verification environment using System verilog UVM. Knowledge on both subsystem level and SOC verification. Expertise in Flow setup using scripting languages Perl, Python, Make file and Shell Scripts.
Publications in international conferences on ASICverification methodology and verification flow.