VSD - Signal Integrity (Udemy.com)
VLSI - Real and practical steps to build chip with minimum Signal Integrity issues!!
Created by: Kunal Ghosh
Last updated January 2017
What you will learn
- To Learn Chip Design with minimal Crosstalk in the circuits.
- To Design a Chip with minimal errors.
How it compares
Against the other 335 rated Udemy courses in Engineering on CourseDuck:
- Rating4.5 out of 5higher than 55% of them
- Reviews576#137 of 336 by number of reviews
- Length6.6 hourslonger than 61% of them
- Last updatedJanuary 2017earlier than 96% of them
Course Description
Crosstalk is the interference caused due to communication between the circuits
Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.
Course Details:
Reasons for Crosstalk
Introduction to Noise Margin
Crosstalk Glitch Example
Factors Affecting Glitch Height
AC Noise Margin
Timing Window Concepts
Impact of Crosstalk on Setup and Hold Timing
Techniques to reduce Crosstalk
Power Supply Noise Who this course is for:
- VLSI Engineers keen to Learn Backend of Chip Design
- Physical Design Engineer
- Students Learning VLSI Engineering
Instructor Details
- 4.5 Rating
576 Reviews
Kunal Ghosh
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal heldseveral technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.
Hands on with Technology @
1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP's and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.
2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.
3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer
4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.
5) "IR aware STA"
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Reviews
I found this course very informative. Kunal has explained the xtalk concept and xtalk/Signal integrity avoidance/prevention very well.
It's worth taking this course.
Thanks Kunal, you have captured the industry concepts very well for a beginner. I have advised this course to many students, wanting to enter the industry.
Great work again
-Employee from ANSYS
Really basic course - an Electronic Engineer should really know at least 90% of this course coming out from University. Definitely not for a VLSI Engineer or a Physical/Backend engineer - maybe good for students who did not follow digital design courses. Instructor makes good examples and analogies, but he spends a lot of time repeating the same things; he could shrink three or four lessons into a single one. Also, he should improve his spoken English: for example, the number "1" is said /wan/, not /van/!
I was expecting much more from an online course sold at 95 Euro, sorry.
Quality Score
No CourseDuck member has rated this course yet. Taken it? Give each part a thumbs up or down.
Overall Score : 90 / 100









