VSD - Signal Integrity (Udemy.com)
VLSI - Real and practical steps to build chip with minimum Signal Integrity issues!!
Created by: Kunal Ghosh
Produced in 2014
What you will learn
- To Learn Chip Design with minimal Crosstalk in the circuits.
- To Design a Chip with minimal errors.
Quality Score
Overall Score : 84 / 100
Course Description
Crosstalk is the interference caused due to communication between the circuits
Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.
Course Details:
Reasons for Crosstalk
Introduction to Noise Margin
Crosstalk Glitch Example
Factors Affecting Glitch Height
AC Noise Margin
Timing Window Concepts
Impact of Crosstalk on Setup and Hold Timing
Techniques to reduce Crosstalk
Power Supply Noise Who this course is for:
- VLSI Engineers keen to Learn Backend of Chip Design
- Physical Design Engineer
- Students Learning VLSI Engineering
Instructor Details
- 4.2 Rating
47 Reviews
Kunal Ghosh
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal heldseveral technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.
Hands on with Technology @
1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP's and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.
2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.
3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer
4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.
5) "IR aware STA"
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Reviews
- Video Duration:
6.5h - Price: 11.99 Track Price 11.99 Track Price
- Provider: Udemy
- Year:
2014 - Language:
English, English [Auto-generated] - Certificate:
Yes
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